programmable clock
英 [ˈprəʊɡræməbl klɒk]
美 [ˈproʊɡræməbl klɑːk]
网络 可编程时钟
双语例句
- Application of Programmable Logic-function Device GAL in the Design of Digital Electronic Clock
可编程逻辑器件GAL在设计数字式电子时钟中的应用 - Circuits for programmable clock generators
可编程的时钟发生器 - Through the programmable logic device ( PLD), the first-in first-out ( FIFO)'s four precise clock and write enabling signals can be achieved, thus the accuracy of the whole system and flexibility of the time delay are increased.
通过PLD能够得到FIFO4路精确的时钟和读写使能信号，从而提高了整个系统的工作时钟精确度和延时的灵活性。 - We introduce an on-chip clock synchronous method, in which programmable delays are in-serted in the clock distribution network, such that clock alignment and synchronization are achieved.
本文介绍了一种SoC时钟同步设计方法，这种方法将可调节延时的时钟电路插入在时钟分布网络中，以取得时钟边沿的匹配和同步。 - Design of a high efficient programmable clock
一种高效的可编程时钟源设计 - Some analytical results are also presented. In the camera design, programmable logic devices are used to implement high-speed part of circuits, especially, CCD clock generators and access control modules for FIFO, dual-port RAM, and flash memory.
为使相机具有紧凑的结构，本文使用了可编程逻辑电路实现相机控制电路中的高速部分，特别是CCD工作时钟发生器、FIFO、双端口RAM及闪存等读写控制电路。 - The experimental result certifies that this programmable clock has many advantages, such as high precision, good stability.
实验结果验证了该时钟源具有精度高、稳定性好等优点。 - A digital phase-shifting frequency-dividing clock has been designed with CPLD ( Complex Programmable Logic Device) technique which modularizes hardware circuit and integrates different modules into one chip.
设计了一种数字移相分频钟，其中利用了先进的复杂可编程逻辑器件（CPLD-ComplexProgrammableLogicDevice）技术，将硬件电路模块化，把各功能模块集成在一个芯片中。 - Through controlling an N-bit accumulator and then get its highest bit to generate the programmable clock.
通过控制一个N位累加器累加，取其最高位，即可得到可编程时钟源。 - Flexible auto-switching way is realized by using programmable logic technology, communication network by Ethernet, and hardware clock synchronization by GPS ( Global Position System) technology.
利用以太网方式实现了通信组网；利用全球定位系统（GPS）技术实现了硬件对时功能。 - Also, a digital audio frequency programmable frequency synthesizer can be designed with frequency range being controlled to f 0/ 2~ f 0/ 2N for a clock of f 0.
另外，还可设计出一种数字音频程控频率合成器，时钟为f0时，可控频率范围为f02～f02N。 - Each ACE includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and ( 216-1).
每一个集成异步通信器件包括一个可编程的波特率发生器，它能够对输入时钟进行1～216-1的分频。 - The PLL frequency synthesizer designed has very wide operating frequency range and programmable ability. Its output frequency points are to meet demand for clock of very scalar video signal processing integrated circuit.
所设计的PLL频率合成器具有较宽的频带和编程能力，输出频率多达二十八个频点，满足大规模视频图象处理芯片对时钟的要求。